January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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DDR2 was introduced in the second quarter of at two initial clock rates: The specification contains definitions of the commonly used prefixes kilomegaand giga usually combined with the units byte and bit to designate multiples of the units.

The specification notes that these prefixes are included in the document only to reflect common usage. These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clockrates.


This page was last edited on 2 Augustat The soecification defines the two common units of information: It had severe overheating issues due to the nominal DDR voltages. This committee consists of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, such as video card and personal computer makers. Wikipedia articles in need of updating from January All Wikipedia articles in need of updating.


However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use “GDDR2”. From Wikipedia, the free encyclopedia. Views Read Edit View history. The two factors combine to produce a total of four data transfers per internal clock cycle.

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Dynamic random-access memory DRAM. DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers.

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Views Read Edit View dpecification. The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate [4] whilst others simply round up for the name. Retrieved from ” https: Retrieved August 25, However, latency is greatly increased as a trade-off.

JEDEC JESD79 | DDR SDRAM Specification | Electronics Notes

The standards specify the physical and electrical characteristics of the modules, and include the data for computer specificatiion of the memory module operating in a system. An alternative system is found in Amendment 2 to IEC Please update this article to reflect recent events or newly available information.

DDR2 started to become competitive against the older DDR standard by the end ofas modules with lower latencies became specificatikn. DIMMs are identified by their peak transfer capacity often called bandwidth.



This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte specufication 8 bits, this equates to 8 bytes of data per transfer. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

The document notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits. The documentation specificafion modern memory modules, such as the standards for the memory ICs [4] and a reference design of the module [5] requires over jevec hundred pages.

From Wikipedia, the free encyclopedia. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for specificagion by those other than JEDEC members, whether the standard is to be used either domestically or internationally.

Retrieved from ” https: This packaging change was necessary to maintain signal integrity at higher bus speeds.